1. Field of the Invention
The present invention relates to a video signal control circuit that, receiving a video signal obtained by decoding a composite video signal outputted from a VTR (video tape recorder) or the like, outputs to regulate the pixel number for each line of the video signal into a constant number.
2. Description of the Related Art
Generally, the video signal reproduced by a VTR contains jitters. Accordingly, the pixel number per one line of the video signal often varies in dispersion by about (1˜2) from the standard pixel number (for example, the pixel number of the NTSC signal conformable to ITU-R-601 is 858 per one line).
In a video decoder, when such a video signal reproduced by a VTR (hereunder, referred to as a non-standard signal) as it stands is decoded in accordance with the horizontal synchronous signal and the vertical synchronous signal, the decoded output also contains jitters. Accordingly, a further processing of such decoded data has involved a problem that the edge of the processed image becomes uneven, or a problem that the video signal processing is failed at the subsequent stage. Therefore, in a conventional method, a decoded signal by the video decoder is temporarily written in a frame memory or the like in accordance with the horizontal synchronous signal, and a written signal is read out in accordance with a specific horizontal synchronous signal of a constant period. Thus, the pixel number per one line has been regulated into the standard pixel number.
There has been another method that regulates the pixel number per one line into a constant one, as follows. The non-standard signal is equalized on the time base by means of a PLL (phase lock loop) circuit or the like to be converted into a signal having the period of an average frequency of the non-standard signal, thus the pixel number per one line is regulated to be constant. In this method, however, the pixel number per one line can be regulated constant; but there can be a delicate discrepancy between the period of the average frequency and the period of the timing signal in the video decoder, which has created a problem. Accordingly, the signal whose pixel number per one line is made constant by using the PLL circuit or the like is temporarily written in a frame memory, etc., again. The written signal is read out in accordance with the specific horizontal synchronous signal of a constant period, thereby the pixel number per one line has been regulated into the standard pixel number.
However, in case of the method that regulates the pixel number per one line to be constant by using the foregoing frame memory, there has been a problem that the circuit configuration becomes complicated and the circuit scale becomes huge.
It is therefore an object of the present invention to provide a video signal control circuit that solves these disadvantages of the conventional technique, and regulates the pixel number per one line into a constant with a simplified circuit configuration, without using a large capacity memory such as the frame memory.